<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>Allegro &#8211; 无线时代</title>
	<atom:link href="https://www.witimes.net/tag/allegro/feed/" rel="self" type="application/rss+xml" />
	<link>https://www.witimes.net</link>
	<description>研究WiFi、射频与软件无线电</description>
	<lastBuildDate>Wed, 31 Dec 2025 01:05:51 +0000</lastBuildDate>
	<language>zh-Hans</language>
	<sy:updatePeriod>
	hourly	</sy:updatePeriod>
	<sy:updateFrequency>
	1	</sy:updateFrequency>
	<generator>https://wordpress.org/?v=6.9.4</generator>
	<item>
		<title>Vivado与Cadence冲突的问题</title>
		<link>https://www.witimes.net/vivado-cadence-conflict/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Mon, 20 Oct 2025 02:41:52 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<category><![CDATA[Vivado]]></category>
		<guid isPermaLink="false">https://www.witimes.net/?p=14054</guid>

					<description><![CDATA[今早打开Allegro及Capture CIS时，发现都会出现“应用程序错误”，“应用程序无法正常启动(0xc [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro如何美观的对铜皮开窗</title>
		<link>https://www.witimes.net/allegro-beautiful-soldermask/</link>
		
		<dc:creator><![CDATA[Leon]]></dc:creator>
		<pubDate>Tue, 13 Dec 2022 10:57:01 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">https://greatrf.com/?p=13552</guid>

					<description><![CDATA[相信大家在画PCB时，经常会有对铜皮进行开窗亮铜皮处理，以便更好的导热和散热，但会遇到非GND网络的过孔，需使 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro过孔重叠却不报DRC错误的解决办法</title>
		<link>https://www.witimes.net/allegro-overlapped-vias-no-drc/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Fri, 02 Apr 2021 01:48:50 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">https://greatrf.com/?p=13318</guid>

					<description><![CDATA[去年在设计一款无线产品的时候，为了节省时间，使用了别人设计好的PCB源文件，结果遇到了一件有意思的事情——Al [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro PCB设计模板的建立与使用</title>
		<link>https://www.witimes.net/allegro-create-template/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Thu, 29 Oct 2015 00:58:42 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">https://www.zencheer.com/?p=9185</guid>

					<description><![CDATA[用过Allegro的读者一定知道，Allegro中有大量的颜色设定命令，大量的约束条件，而且在出Gerber文 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro中设置等长规则的通用方法</title>
		<link>https://www.witimes.net/allegro-create-match-group/</link>
					<comments>https://www.witimes.net/allegro-create-match-group/#comments</comments>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Fri, 24 Jul 2015 00:44:09 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=8012</guid>

					<description><![CDATA[在当今高速PCB设计中，一组走线的等长越来越重要。Allegro为工程师提供了功能强大的Constrain M [&#8230;]]]></description>
		
					<wfw:commentRss>https://www.witimes.net/allegro-create-match-group/feed/</wfw:commentRss>
			<slash:comments>3</slash:comments>
		
		
			</item>
		<item>
		<title>Allegro中设置开窗的方法</title>
		<link>https://www.witimes.net/allegro-soldermask/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Thu, 08 Jan 2015 05:33:13 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=7053</guid>

					<description><![CDATA[最近常常看到读者在本站搜索Allegro开窗相关的内容， 笔者特撰写本文简单介绍一下。Allegro开窗其实就 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro导入DXF的方法</title>
		<link>https://www.witimes.net/allegro-import-dxf/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Mon, 01 Dec 2014 13:10:07 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=6876</guid>

					<description><![CDATA[EDA工程师在PCB设计过程中，往往需要与结构工程师打交道，结构图纸即DXF文件就是结构工程师与EDA工程师沟 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro修改dra封装的引脚编号</title>
		<link>https://www.witimes.net/allegro-pin-number/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Fri, 28 Nov 2014 05:24:42 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=6622</guid>

					<description><![CDATA[在Allegro中，有这样一种情况：一个dra封装已经创建完成，但是不小心排错了引脚顺序，需要修改为正确的。我 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>Allegro中如何导入Outline</title>
		<link>https://www.witimes.net/allegro-import-outline/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Wed, 26 Nov 2014 12:50:36 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=6604</guid>

					<description><![CDATA[在PCB设计过程中，EDA工程师常常需要匹配两代PCB的结构，这种情况下，将上一代PCB的Outline（板框 [&#8230;]]]></description>
		
		
		
			</item>
		<item>
		<title>使用Allegro从brd文件中导出封装及焊盘的方法</title>
		<link>https://www.witimes.net/allegro-export-package/</link>
		
		<dc:creator><![CDATA[lics]]></dc:creator>
		<pubDate>Mon, 29 Sep 2014 02:38:33 +0000</pubDate>
				<category><![CDATA[技术文章]]></category>
		<category><![CDATA[Allegro]]></category>
		<guid isPermaLink="false">http://www.beamsky.com/?p=6243</guid>

					<description><![CDATA[最近常常看到网友的提问“Allegro如何导出封装”，“为什么Allegro导出的封装没有焊盘”等，本文给出A [&#8230;]]]></description>
		
		
		
			</item>
	</channel>
</rss>
